(a) Field of the Invention
The present invention relates to a drive apparatus and method for a plasma display panel. More particularly, the present invention relates to a drive apparatus and method for a plasma display panel in which the drive apparatus and method improve contrast and prevent mis-discharge.
(b) Description of the Related Art
Flat display devices such as the liquid crystal display (LCD), the field emission display (FED), and the plasma display panel (PDP) have recently been undergoing rapid development. The PDP has some advantages over the other flat display configurations, such as in higher brightness, better illumination efficiency, and a wider viewing angle. Accordingly, many anticipate the PDP to replace the cathode ray tube (CRT) for displays having screen sizes of 40 inches or greater.
The PDP is a display device that utilizes plasma generated by gas discharge to realize the display of characters or images. The PDP includes a configuration in which many hundreds to many thousands of pixels (depending on the size of the PDP) are arranged in a matrix. PDPs are classified into the two different types of the DC PDP and AC PDP depending on the drive voltage waveform and discharge cell structure.
In the DC PDP, electrodes are fully exposed in a discharge space such that current flows in the discharge space while voltage is being applied. As a result, resistance for limiting the flow of current must be provided. On the other hand, in the AC PDP, the electrodes are covered with a dielectric layer such that current is limited through the formation of a natural capacitance. As a result, the electrodes are protected from the collision of ions so that the AC PDP has a longer life span.
FIG. 1 is a partial perspective view of an AC PDP.
As shown in the drawing, scan electrodes 4 and sustain electrodes 5 are provided in parallel pairs on a first glass substrate 1, and they are covered by a dielectric layer 2 and a protection film 3. A plurality of address electrodes 8 is provided on a second glass substrate 6, and they are covered with an insulating layer 7. Also, barrier ribs 9 are formed on the insulating layer 7 at areas corresponding to and between the address electrodes 8 and in parallel to the same. Phosphor layers 10 are formed on the insulating layer 7 between the barrier ribs 9. The first glass substrate 1 and the second glass substrate 6 are mounted opposing one another while forming a discharge space 11 therebetween and in such a manner that the scan electrodes 4 and the sustain electrodes 5 are orthogonal to the address electrodes 8. Areas of the discharge space where the address electrodes 8 intersect the pairs of the scan electrodes 4 and sustain electrodes 5 form discharge cells 12.
FIG. 2 schematically shows an electrode arrangement for a plasma display panel.
As shown in the drawing, the PDP electrodes have an m×n matrix configuration. In more detail, the address electrodes (A1–Am) are arranged in the column direction, while n-rows of scan electrodes (Y1–Yn) and sustain electrodes (X1–Xn) are alternately arranged in the row direction. The scan electrodes will hereinafter be referred to as “Y electrodes” and the sustain electrodes will be referred to as “X electrodes”. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 of FIG. 1.
FIG. 3 is a drive waveform of a conventional plasma display panel.
As shown in the drawing, each sub-field is divided into a reset interval, an address interval, and a sustain interval according to the conventional drive method for a PDP. In the reset interval, a wall charge state of a previous sustain discharge is eliminated, and a wall charge is set up to stably perform a subsequent address discharge. The address interval is a period of time during which cells that are on and cells that are off in the panel are selected, and an operation is performed so that wall charges accumulate in cells that are on (cells that are addressed). Further, in the sustain interval, discharge is performed to display an image in the cells that are addressed.
The conventional operations in the reset interval will now be described in more detail. With reference to FIG. 3, the conventional reset interval includes an elimination interval, a Y ramp ascending interval, and a Y ramp descending interval.
(1) Elimination Interval
After a final sustain discharge is completed, a (+) electric charge and a (−) electric charge are accumulated respectively in the X electrodes and the Y electrodes.
Following the completion of the sustain discharge, an elimination ramp voltage that gently increases from 0V to +Ve(V) is applied to the X electrodes. Accordingly, a wall charge formed in the X electrodes and the Y electrodes is gradually eliminated.
(2) Y Ramp Ascending Interval
In the Y ramp ascending interval, the address electrodes and the X electrodes are maintained at 0V, and a ramp voltage gently increasing from voltage Vs to voltage Vset is applied to the Y electrodes. While the ramp voltage is increasing, a first weak reset discharge occurs from the Y electrodes to the address electrodes and to the X electrodes in all discharge cells. As a result, a (−) wall charge is accumulated in the Y electrodes, and a (+) wall charge is accumulated in the address electrodes and the X electrodes.
(3) Y Ramp Descending Interval
In a second half of the reset interval and in a state where the X electrodes are maintained at a constant voltage Ve, a ramp voltage gently decreasing from voltage Vs to 0V is applied to the Y electrodes. While this ramp voltage is decreasing, a second weak reset discharge occurs, again in all the discharge cells.
According to the conventional reset method shown in FIG. 3, the reset discharge occurs in the Y ramp ascending interval and the Y ramp descending interval such that the amount of wall discharge in the cells is adjusted. Accordingly, a precise addressing operation occurs in a subsequent address interval. At this time, the larger the voltage difference between the Y electrodes and the X electrodes, the greater the precision in the addressing operation in the subsequent addressing interval.
However, with the conventional reset method shown in FIG. 3, Vset, which is a high voltage of approximately 380V, is applied to the Y electrodes, while the ground voltage is supplied to the X electrodes. Therefore, an unnecessarily high voltage is applied between the X electrodes and the Y electrodes such that a strong discharge occurs, thereby deteriorating the contrast of the PDP.